SI5347_16 Datasheet, PDF (24/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Electrical Specifications
Table 5.2. DC Characteristics
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Core Supply Current^{1, 2}
I_DD
Si5347, 4 DSPLLs
—
300
450
mA
S5347, 1 DSPLL
—
190
340
mA
Si5346
—
185
280
mA
I_DDA
Si5347, 4 DSPLLs
—
125
140
mA
Si5347, 1 DSPLL
—
125
140
mA
Si5346
—
125
140
mA
Output Buffer Supply Current
I_DDO
LVPECL Output³
—
22
26
mA
@ 156.25 MHz
LVDS Output³
—
15
18
mA
@ 156.25 MHz
3.3 V LVCMOS⁴ Output
—
22
30
mA
@ 156.25 MHz
2.5 V LVCMOS⁴ Output
—
18
23
mA
@ 156.25 MHz
1.8 V LVCMOS⁴ Output
—
12
16
mA
@ 156.25 MHz
Total Power Dissipation⁵
P_d
Si5347, 4 DSPLLs¹
—
1200
1600
mW
Si5347, 1 DSPLL¹
—
1050
1420
mW
Si5346²
—
880
1100
mW
Notes:
1. Si5347 test configuration: 7×2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2. Si5346 test configuration: 4×2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3. Differential outputs terminated into an AC coupled 100 Ω load.
4. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV
= 3, which is the strongest driver setting. Refer to the Si5347/46 Family Reference Manualfor more details on register settings.
5. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is
not available. All EVBs support detailed current measurements for any configuration.
Differential Output Test Configuration
IDDO
OUT
OUTb
0.1 µF
50
100
50
0.1 µF
IDDO
OUT
OUTb
LVCMOS Output Test Configuration
Trace length 5
inches
50
499
0.1 µF
4.7 pF
56
50 Scope Input
499
0.1 µF
50
50 Scope Input
4.7 pF
56
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