SI5347_16 Datasheet, PDF (20/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Functional Description
3.8.14 Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable
phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same
result.
3.9 Power Management
Unused inputs, output drivers, and DSPLLs can be powered down when unused. Consult the Si5347/46 Family Reference Manual and
ClockBuilder Pro configuration utility for details.
3.10 In-Circuit Programming
The Si5347/46 is fully configurable using the serial interface (I²C or SPI). At power-up the device downloads its default register values
from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to gen-
erate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power sup-
ply voltages applied to its V_DD and V_DDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the
old configuration is no longer accessible. Refer to the Si5347/46 Family Reference Manual for a detailed procedure for writing registers
to NVM.
3.11 Serial Interface
Configuration and operation of the Si5347/46 is controlled by reading and writing registers using the I²C or SPI interface. The I2C_SEL
pin selects I²C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or
3-wire mode. See the Si5347/46 Family Reference Manual for details.
3.12 Custom Factory Preprogrammed Parts
For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered
with a specific configuration written into NVM. A factory pre-programmed part will generate clocks at power-up. Custom, factory-pre-
programmed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly
and easily request and generate a custom part number for your configuration.
In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your
design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local
Silicon Labs sales representative. Samples of your pre-programmed device will typically ship in about two weeks.
3.13 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices
As with essentially all modern software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.si-
labs.com, you will be notified whenever changes are made and what the impact of those changes are. This update process will ulti-
mately enable ClockBuilder Pro users to access all features and register setting values documented in this data sheet and the Si347/46
Family Reference Manual.
However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register
setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assis-
tance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock
outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your CBPro
project file with your specific features and register settings enabled using what is referred to as the manual "settings override" feature of
CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro
design report are shown in the table below.
Table 3.2. Setting Overrides
Location
0x0535[0]
0x0B48[4:0]
Name
FORCE_HOLD_PLLB
OOF_DIV_CLK_DIS
Type
No NVM
User
Target
N/A
OPN and EVB
Dec Value
1
31
Hex Value
0x1
0x1F
Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the
NVM file. The flowchart for this process is shown in the figure below.
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