SI5347_16 Datasheet, PDF (28/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Electrical Specifications
Table 5.6. LVCMOS Clock Output Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Output Frequency
Duty Cycle
Output-to-Output Skew
Output Voltage High^1,2,3
Output Voltage Low^1,2,3
LVCMOS Rise and Fall
Times³
(20% to 80%)
Symbol
Test Condition
Min
Typ
f_OUT
0.0001
—
DC
f_OUT <100 MHz
48
—
100 MHz < f_OUT < 250 MHz
45
—
T_SK
When outputs are on same DSPLLs
—
30
V_OH
V_DDO = 3.3 V
OUTx_CMOS_DRV=1 I_{OH =} –10 mA V_DDO x 0.85
—
OUTx_CMOS_DRV=2 I_{OH =} –12 mA
—
OUTx_CMOS_DRV=3 I_{OH =} –17 mA
—
V_DDO = 2.5 V
OUTx_CMOS_DRV=1 I_{OH =} –6 mA V_DDO x 0.85
—
OUTx_CMOS_DRV=2 I_{OH =} –8 mA
—
OUTx_CMOS_DRV=3 I_{OH =} –11 mA
—
V_DDO = 1.8 V
OUTx_CMOS_DRV=2 I_{OH =} –4 mA V_DDO x 0.85
—
OUTx_CMOS_DRV=3 I_{OH =} –5 mA
—
V_OL
V_DDO = 3.3 V
OUTx_CMOS_DRV=1 I_OL = 10 mA
—
—
OUTx_CMOS_DRV=2 I_OL = 12 mA
—
—
OUTx_CMOS_DRV=3 I_OL = 17 mA
—
—
V_DDO = 2.5 V
OUTx_CMOS_DRV=1 I_OL = 6 mA
—
—
OUTx_CMOS_DRV=2 I_OL = 8 mA
—
—
OUTx_CMOS_DRV=3 I_OL = 11 mA
—
—
V_DDO = 1.8 V
OUTx_CMOS_DRV=2 I_OL = 4 mA
—
—
OUTx_CMOS_DRV=3 I_OL = 5 mA
—
—
tr/tf
VDDO = 3.3V
—
400
VDDO = 2.5 V
—
450
VDDO = 1.8 V
—
550
Max
250
52
55
140
—
—
—
—
—
—
—
—
V_DDO x 0.15
V_DDO x 0.15
V_DDO x 0.15
600
600
750
Unit
MHz
%
ps
V
V
V
V
V
V
ps
ps
ps
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