SI5347_16 Datasheet, PDF (42/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Pin Descriptions
Table 9.1. Si5347/46 Pin Descriptions¹
Pin
Name
Inputs
XA
XB
Pin Number
Si5347A/B Si5347C/D
Si5346
8
8
5
9
9
6
X1
7
7
4
X2
10
10
7
IN0
63
63
43
IN0b
64
64
44
IN1
1
1
1
IN1b
2
2
2
IN2
14
14
10
IN2b
15
15
11
IN3
61
61
41
IN3b
62
62
42
Outputs
OUT0
24
24
20
OUT0b
23
23
19
OUT1
31
38
25
OUT1b
30
37
24
OUT2
35
45
31
OUT2b
34
44
30
OUT3
38
51
36
OUT3b
37
50
35
OUT4
45
—
—
OUT4b
44
—
—
OUT5
51
—
—
OUT5b
50
—
—
OUT6
54
—
—
OUT6b
53
—
—
OUT7
59
—
—
OUT7b
58
—
—
Pin
Type²
Function
I
Crystal Input. Input pin for external crystal (XTAL). Alter-
natively these pins can be driven with an external refer-
I
ence clock (REFCLK). An internal register bit selects
XTAL or REFCLK mode. Default is XTAL mode.
I
XTAL Ground. Connect these pins directly to the XTAL
ground pins. X1, X2, and the XTAL ground pins should be
I
separated from the PCB ground plane. Refer to the
Si5347/46 Family Reference Manual for layout guidelines.
These pins should be left disconnected when connecting
XA/XB pins to an external reference clock (REFCLK).
I
Clock Inputs. These pins accept an input clock for syn-
chronizing the device. They support both differential and
I
single-ended clock signals. Refer to 3.6.4 Input Configura-
I
tion and Terminations for input termination options. These
pins are high-impedance and must be terminated external-
I
ly. The negative side of the differential input must be
grounded when accepting a single-ended clock.
I
I
I
I
O
Output Clocks. These output clocks support a program-
mable signal amplitude and common mode voltage. De-
O
sired output signal format is configurable using register
O
control. Termination recommendations are provided in
3.8.2 Differential Output Terminations and 3.8.3 LVCMOS
O
Output Terminations. Unused outputs should be left un-
connected.
O
O
O
O
O
O
O
O
O
O
O
O
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