SI5347_16 Datasheet, PDF (14/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Functional Description
LOL
LOCKED
0
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
Hysteresis
Lost Lock
0.1
1
Phase Detector Frequency Difference (ppm)
10,000
Figure 3.12. LOL Set and Clear Thresholds
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input
clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The
configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using
the ClockBuilderPro utility.
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