SI5347_16 Datasheet, PDF (8/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Functional Description
3.6 Inputs (IN0, IN1, IN2, IN3)
There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both differential and single-ended clocks.
A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs, as shown in the figure
below.
Si5347
IN0
IN0b
÷
P0n
P0d
Input
Crosspoint
0
1
2
3
DSPLL
A
IN1
IN1b
÷
P1n
P1d
0
1
DSPLL
2
B
3
IN2
IN2b
÷
P2n
P2d
0
1
DSPLL
2
C
3
IN3
IN3b
÷
P3n
P3d
0
1
DSPLL
2
D
3
Figure 3.4. DSPLL Input Selection Crosspoint
3.6.1 Input Selection
Input selection for each of the DSPLLs can be made manually through register control or automatically using an internal state machine.
3.6.2 Manual Input Selection
In Manual Mode, the input selection is made by writing to a register. If there is no clock signal on the selected input, the DSPLL will
automatically enter Holdover Mode.
3.6.3 Automatic Input Selection
When configured in this mode, the DSPLL automatically selects a valid input that has the highest configured priority. The priority
scheme is independently configurable for each DSPLL and supports revertive or non-revertive selection.
All inputs are continuously monitored for loss of signal (LOS) and/or invalid frequency range (OOF). Only inputs that do not assert both
the LOS and OOF monitors can be selected for synchronization by the automatic state machine. The DSPLL(s) will enter the Holdover
mode if there are no valid inputs available.
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