SI5347_16 Datasheet, PDF (4/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

Si5347/46 Rev D Data Sheet
Functional Description
3. Functional Description
The Si5347 takes advantage of Silicon Labs’ 4^th generation DSPLL technology to offer the industry’s most integrated and flexible jitter
attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common
serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) with manual or automatic input selection. Any of the
output clocks (OUT0 to OUT7) can be configured to any of the DSPLLs using a flexible crosspoint connection. The Si5346 is a smaller
form factor dual DSPLL version with four inputs and four outputs.
3.1 Frequency Configuration
The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile
memory. The combination of fractional input dividers (P_n/P_d), fractional frequency multiplication (M_n/M_d), and integer output division
(R_n) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a spe-
cific frequency plan are easily determined using the ClockBuilder Pro utility.
3.2 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register-configurable DSPLL loop bandwidth set-
tings in the range of 0.1 Hz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally,
each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.
3.2.1 Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-
ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock
acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting, as described in
Section 3.2 DSPLL Loop Bandwidth. The fastlock feature can be enabled or disabled independently for each of the DSPLLs.
3.3 Modes of Operation
Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition
Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation
on page 4. The following sections describe each of these modes in greater detail.
3.3.1 Initialization and Reset
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard
reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-
stored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard register
reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all
DSPLLs, while a soft reset can either affect all or each DSPLL individually.
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