SI5347_16 Datasheet, PDF (17/55 Pages) Silicon Laboratories – Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenuators

3.8.2 Differential Output Terminations
Si5347/46 Rev D Data Sheet
Functional Description
Note: In this document, the terms "LVDS" and "LVPECL" refer to driver formats that are compatible with these signaling standards.
The differential output drivers support both ac-coupled and dc-coupled terminations, as shown in the figure below.
DC-coupled LVDS
VDDO = 3.3V, 2.5V, 1.8V
50
OUTx
OUTxb
100
50
Si5347/46
AC-coupled LVDS/LVPECL
VDDO = 3.3V, 2.5V, 1.8V
50
OUTx
OUTxb
100
50
Si5347/46
Internally
self-biased
AC-coupled HCSL
VDDO = 3.3V, 2.5V, 1.8V
R1
R1
OUTx
50
OUTxb
50
Si5347/46
R2
R2
VDDRX
Standard
HCSL
Receiver
AC-coupled LVPECL
VDDO = 3.3V, 2.5V
VDD – 1.3V
50
50
OUTx
50
OUTxb
50
Si5347/46
For VCM = 0.35V
VDDRX
3.3 V
2.5 V
1.8 V
R1
R2
442 Ohm 56.2 Ohm
332 Ohm 59 Ohm
243 Ohm 63.4 Ohm
Figure 3.15. Supported Differential Output Terminations
3.8.3 LVCMOS Output Terminations
LVCMOS outputs are dc-coupled, as shown in the figure below.
DC Coupled LVCMOS
VDDO = 3.3 V, 2.5 V, 1.8 V
OUTx
Rs
OUTxb
3.3 V, 2.5 V, 1.8 V
LVCMOS
50
Si5347/46
50
Rs
Figure 3.16. LVCMOS Output Terminations
3.8.4 Output Signal Format
The differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal
formats, including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS
(3.3 V, 2.5 V, or 1.8 V) drivers providing up to 16 single-ended outputs or any combination of differential and single-ended outputs.
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