S5D0127X01 Datasheet, PDF (91/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
Characteristics
Symbol
Digital I/O Characteristics
Input low voltage (other digital I/O)
Input high voltage (other digital I/O)
Input low voltage (SCLK,SDAT,RST)
Input high voltage (SCLK,SDAT,RST)
Input low current (V_IN = 0.4 V)
Input high current(VIN=2.4)
Digital output low voltage (I_OL=3.2mA)
Digital output high voltage (IOH=400µA)
Digital three-state current
Digital output capacitance
Maximum capacitance load for digital data pins
Maximum capacitance load for CK and CK2
outputs
V_IL
V_IH
V_ILI2C
V_IHI2C
I_IL
I_IH
V_OL
V_OH
I_OZ
C_OUT
C_L-DATA
C_L-CK
Timing Characteristics - Digital Inputs
XTALI input pulse width low
XTALI input pulse width high
Clock and Data Timing
t_pwlX
t_pwhX
Analog video input to digital video output delay t_dCHIP
Pulse width high for CK (KS0112 operates at t_pwhCK
frequencies from 24.5 MHz to 29 MHz)
Pulse width high for CK2
t_pwhCK2
Delay from rising edge of CK to CK2
t_CK2
Delay from rising edge CK to data change
t_dD
(including pins Y0-Y7, C0-C7, HAV, VAV, EHAV, _{(CK is output)}
EVAV, HS1, HS2, VS, ODD, PID, SCH)
t_dD
(CK is input)
Minimum hold time from rising edge of CK for t_hD
data output)
Delay from falling edge of OEN to data bits in t_zD
3-state
Delay from rising edge OEN to data bits
t_enD
enabled
Timing Characteristics -IIC Host Interface
SCLK clock frequency
Capacitive load for each bus line
Hold time for START condition
Setup time for STOP condition
Rise and fall times for SCLK and SDAT
r_SCLK
C_b
t_hSTA
t_sSTO
t_R, t_F
Min
VSS-0.5
2.0
VSS-0.5
0.7VDD
2.4
15
15
15
30
7
0
0.6
0.6
20
MULTIMEDIA VIDEO
Typ
Max
Units
0.8
V
VDD+0.5
V
0.3VDD
V
VDD+0.5
V
-1
µA
-1
µA
0.4
V
V
50
µA
7
pF
30
pF
60
pF
20
ns
20
ns
120
CK
18.5
22
ns
37
44
ns
4
ns
16
23
ns
14
21
ns
ns
20
ns
18
ns
400
kHz
400
pF
µs
µs
300
ns
ELECTRONICS
Modified on May/04/2000
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