S5D0127X01 Datasheet, PDF (54/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Index Mnemonic
04h
CMDD
bit 7
EAV
Control Register D
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
CKDIR
INPSL[1:0]
SYNDIR Y1MHZ GPPORT
GPPORT
Y1MHZ
SYNDIR
INPSL[1:0]
CKDIR
EAV
General purpose port. This register is useful only if DATAA[2:0] == 7. If DIRA == 0, this bit is
read only and reflects the logic state at PORTA pin. If DIRA == 1, any value written to this bit will
appear at PORTA pin.
Luma bandwidth control.
0
Luma bandwidth is controlled by other luma filters in the luma path.*
1
Luma data is low pass filtered to 1MHz bandwidth.
HS1 and VS pin direction control.
0
HS1 and VS are output.*
1
HS1 and VS are input.
Video input and clock source select.
0
Video source is analog and connected to the chip’s analog input. Clock is internally
generated.*
1
Video source is 8-bit digital CbYCr and connected to EXV0 through EXV7 pins.
3
Video source is 8-bit digitized CVBS and connected to EXV0 through EXV7 pins.
Clock select.
0
Clock is from internal clock generator. A reference clock at XTALI pin is required.*
1
Clock is from CK pin. When this is selected, the CK pin automatically becomes an
input.
In 8-bit digital CbYCr input mode, this bit selects the sync source.
0
Horizontal and vertical syncs are from HS1 and VS pins, respectively.*
1
Syncs are embedded in the 8-bit digital data stream (CCIR 656 compatible).
ELECTRONICS
Modified on May/04/2000
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