S5D0127X01 Datasheet, PDF (14/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Table 4: Horizontal Timing Signal Edge Locations (in # of CK)
Description
Chip delay
Sync gate (1-CK pulse)
Back porch gate
Color burst gate (1-CK pulse)
Wide color burst gate
Two pulses per line (1-CK each
pulse)
Default one pulse per line
Default one pulse per line
Default horizontal cropping
Signal
60 Hz
50 Hz
CCIR 601 Square Pixel CCIR 601 Square Pixel
(modulo 1716) (modulo 1560) (modulo 1728) (modulo 1888)
120
120
120
120
SYG
72
72
72
72
BPG
[147 222]
[129 204]
[154 234]
[168 254]
CBG
222
204
234
254
CBGW [159 254]
[147 233]
[173 254]
[186 277]
FH2
42, 900
42, 822
42, 906
42, 986
HS1
HS2
HAV
[65 238]
[65 238]
[351 75]
[45 220]
[45 220]
[334 58]
[69 250]
[69 250]
[379 91]
[65 270]
[65 270]
[415 59]
An additional signal, HAV, is provided for horizontal video cropping. This signal has programmable polarity, start
and stop locations. Two 11-bit registers, HAVB and HAVE, are used to define the first and last pixel locations of the
horizontal portion of the cropped video. Numbers programmed into these registers are used as offset to the default
locations as shown in Table 4. Note that even though HAVB and HAVE have 1-CK resolution, the difference
between them should be maintained at multiple of 4 CKs for correct output.
Table 4 shows the default edge locations relative to the midway of the falling edge of the analog horizontal sync.
Note the numbers shown are in multiple of CK clocks. Figure 6 shows the approximate locations for the horizontal
timing signals. Horizontal timing signals used for scaling will be described in Section 1.6.1.
ELECTRONICS
Modified on May/04/2000
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