S5D0127X01 Datasheet, PDF (58/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Index Mnemonic
0Eh PORTAB
bit 7
DIRB
Port A and B Control
bit 6
bit 5
bit 4
DATAB[2:0]
bit 3
DIRA
bit 2
bit 1
bit 0
DATAA[2:0]
DATAA[2:0]
DIRA
DATAB[2:0]
DIRB
Port A data select. For internal gate signal locations.
0
Port A is disconnected from the internal signal path.*
1
Port A is connected to the BPG (back porch gate) signal.
2
Port A is connected to the SYG (sync tip gate) signal.
3
Port A is connected to the CBG (color burst gate) signal.
4
Port A is connected to the CBGW (color burst gate wide) signal. The CBGW is high
for the entire color burst period.
5
Port A is connected to the SLICE (mid way of the sync tip) signal.
6
Port A is connected to the VBI (vertical blanking interval) signal.
7
Port A is connect to the GPPORT bit.
Port A direction control.
0
Port A is configured as input. The input is connected directly to the signal path
selected by DATAA[2:0]. The internally generated gate signal is disconnected from
the signal path.*
1
Port A is an output and is driven by the internally generated signal as selected by
DATAA[2:0].
Port B data select. For internal gate signal locations.
0
Port B is disconnected from the internal signal path.*
1
Port B is connected to the SCH (sync tip to color burst phase) signal.
2
Port B is connected to the FH2 (twice per line pulses) signal.
3
Port B is connected to the FS_PULSE (falling edge of the sync tip) signal.
4
Port B is connected to the VBI_CVBS (VBI raw ADC) signal. This signal is high for
those lines that output data directly from the ADC (not YUV or RGB data).
5
Port B is connected to the VBI_PROC (VBI sliced) signal. This signal is high for
those video lines that output sliced VBI data.
6
Port B is connected to the VS (Vertical Sync) signal.
7
Port B is configured as the RTCO (Real Time Control Output). This single pin serial
interface transmits phase and frequency information to a video encoder so that it
may operate directly from the S5D0127X01 output clock.
Port B direction control.
0
Port B is configured as input. The input is connected directly to the signal path
selected by DATAB[2:0]. The internally generated gate signal is disconnected from
the signal path.*
1
Port B is an output and is driven by the internally generated signal as selected by
DATAB[2:0].
ELECTRONICS
Modified on May/04/2000
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