S5D0127X01 Datasheet, PDF (13/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Field Rate
Pixels/Line (N)
Active Pixels/Line
Active Lines/Frame
Pixel Rate
ADC Sampling Rate
Table 3: Timing for Different Pixel Rates
CCIR 601 Data Rates
M
60
858
720
480
13.5
27
N,B,G,H,I,D,K,K1,L
50
864
720
580
13.5
27
Square Pixel Data Rates
M
N,B,G,H,I,D,K,K1,L
Units
60
50
Hz
780
944
Pixels
640
768
Pixels
480
580
Lines
12.27
14.75
MHz
24.54
29.5
MHz
The time constants for the pixel clock tracking loop can be adjusted with the HFSEL[1:0] bits.
In addition to providing the pixel clock, the S5D0127X01 also outputs various timing signals to indicate the
beginning of a line, a field, and for field and frame identification. All the timing and clock pins may be optionally put
into high impedance state. Three-state of these pins are software controlled and initial state of these pins at power
up is controlled via two configuration pins: 3 and 4.
The S5D0127X01 can generate all the video timing without video input. This enables the S5D0127X01 to be used
as a video timing generator for a system that contains both the S5D0127X01 for live video input and a MPEG
decoder which requires a video timing generator.
1.2.3. Horizontal Timing
The S5D0127X01 creates many internal timing signals aligned to the horizontal sync tip (mid-way of the falling
edge of horizontal sync, typically ADC code 36). These include locations of color burst (CBG, CBGW) used in
chrominance processing, back porch (BPG), and sync tip timing signals (SLICE, FS_PULSE) used for AGC and
clamp functions. SLICE is low whenever the input is below half way level of horizontal sync (typically ADC code
36). FS_PULSE is a single clock pulse coincide with the start of SLICE. One of these internal signals can be made
available at the PORTA or PORTB pin at any time.
The chip outputs two horizontal synchronization signals: HS1 and HS2. The start and stop locations for these
signals are fully programmable. Offset programmed to HSxB, HSxE, and HSxBE0 are added to the default edge
locations as shown in Table 4. Note that there are different modulo numbers for different input video standards and
output pixel rates.
ELECTRONICS
Modified on May/04/2000
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