S5D0127X01 Datasheet, PDF (52/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Control Register B
Index Mnemonic bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
02h
CMDB AGCGN VALIGN AGCOVF AGCFRZ
INSEL[3:0]
INSEL[3:0]
AGCFRZ
AGCOVF
VALIGN
AGCGN
Analog input channel select.
0
AY0 is composite input.*
1
AY1 is composite input.
2
AY2 is composite input.
4
AC0 is composite input.
5
AC1 is composite input.
6
AC2 is composite input.
8
AY0 is luminance input, AC0 is chrominance input.
9
AY1 is luminance input, AC1 is chrominance input.
A
AY2 is luminance input, AC2 is chrominance input.
F
AY2 is luminance input, AC1 is Cb input, AC2 is Cr input.
Freeze the analog AGC for the Y and C paths at their current values.
0
AGC is running. Reading AGC register returns the current AGC gain.*
1
AGC is frozen. Gain can be changed or read with AGC register.
AGC gain control mode.
0
AGC gain tracks to sync tip and back porch delta.
1
If ADC overflows, AGC gain will be reduced (this has higher priority over normal
sync tip - back porch tracking).*
VS edge alignment control.
0
VS leading edge occurs during serration pulses (typically within the first serration
pulse). VS trailing edge is aligned to half line or beginning of the line depending on
the field.*
1
VS leading edge is aligned to half line or beginning of the line depending on the
field. VS trailing edge is always aligned to beginning of the line.
AGC gain calculation.
0
Normal mode. AGC gain calculation is based on sync tip to back porch difference
equal to 68 ADC code.*
1
AGC gain calculation is base on sync tip to back porch difference equal to 54 ADC
code. This will reduce the AGC gain by a factor of 1/1.25 compare to normal mode.
When used in conjunction with PED and RGBH, this effectively increases the input
dynamic range.
ELECTRONICS
Modified on May/04/2000
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