S5D0127X01 Datasheet, PDF (51/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Index Mnemonic bit 7
01h
CMDA POWDN
bit 6
VSE
Control Register A
bit 5
bit 4
HFSEL[1:0]
bit 3
XT24
bit 2
bit 1
PIXSEL MNFMT
bit 0
IFMT
IFMT
MNFMT
PIXSEL
XT24
HFSEL[1:0]
VSE
POWDN
Manual video input standard select. Standard selection can be controlled automatically if
MNFMT=0.
0
Chip is forced to assume input is 50 Hz.*
1
Chip is forced to assume input is 60 Hz.
Manual input format control override. When this bit is 1 the IFMT bit is enabled.
0
The chip determines the input video standard based on the detected field rate:*
NTSC if 60 Hz.
PAL/SECAM if 50 Hz.
1
Input video standard is selected with the IFMT bit.
Select pixel sampling rate.
0
Output data is at square pixel rate.
1
Output data is at CCIR 601 rate.*
Select the external clock reference frequency.
0
External clock is 26.8 MHz.
1
External clock is 24.576 MHz.*
Horizontal tracking loop frequency select.
0
Force loop to very fast.
1
Force loop to fast.
2
Force loop to VCR time constant.*
3
Force loop to TV time constant.
Change the vertical end location of the VS.
0
Line 10/10.5.*
1
Line 9/9.5.
Power down mode.
0
Normal operation.*
1
All chip functions except microprocessor interface and CK/CK2 generation are
disabled. The output of the CK/CK2 pins retains the most recent frequency when
the power down mode is enabled.
ELECTRONICS
Modified on May/04/2000
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