S5D0127X01 Datasheet, PDF (28/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
1.6. SCALING
The S5D0127X01 includes a high quality down scaler. The video images can be down scaled in both horizontal
and vertical direction to an arbitrary size.
1.6.1. Horizontal Scaler
The horizontal scaler uses a 5-tap 32-phase interpolation filter for luma, and a 3-tap 8-phase interpolation filter for
chroma. Scaled pixel data are stored in an on-chip FIFO so they can be sent out in a continuous stream.
Horizontal scaling ratio is programmed via the 15-bit register HSCL. The timing signal EHAV is used to indicate
when scaled pixel data is available at the video output port. EHAV can be programmed so that it is active for every
line regardless of vertical cropping and scaling. Or it can be programmed to be active only for valid video lines. For
example, Figure 23 shows the timing for CIF output assuming HAV is programmed to be active for 720 pixels. The
HSCL register is programmed with the value 4000 (hex). The trailing edge of EHAV is either aligned with the trailing
edge of HAV if the total number of scaled pixels is even, or is one pixel clock earlier if the number is odd.
CK2
HAV
EHAV
Y[7:0]
C[7:0]
720
360
Y₀
Y₁
Y₂
Y₃
-
U₀ V₀
U₂
V₂
-
-
Y₃₅₆ Y₃₅₇ Y₃₅₈ Y₃₅₉
-
U₃₅₆ V₃₅₆ U₃₅₈ V₃₅₈
Figure 23. Horizontal Scaler Timing for CIF Output (CCIR 601 Pixel Rate)
Frequency response and group delay for the luma scaler are shown in Figure 24 and Figure 25, respectively. The
luma interpolation filter is designed to achieve relatively flat frequency response and minimal group delay up to the
normal video bandwidth. A flat full data path frequency response may be obtained with the help of the luma
peaking control register HYPK[1:0]. The high quality filter ensures minimal artifacts for any scaling ratio.
ELECTRONICS
Modified on May/04/2000
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