S5D0127X01 Datasheet, PDF (53/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Index Mnemonic
03h
CMDC
bit 7
VMEN
bit 6
TSTGE1
Control register C
bit 5
bit 4
bit 3
0
TSTGPK TSTGPH
bit 2
bit 1
TSTGFR[1:0]
bit 0
TSTGEN
TSTGEN
TSTGFR[1:0]
TSTGPH
TSTGPK
TSTGE1
VMEN
Enable manual control of horizontal phase and frequency tracking.
0
Auto phase and frequency tracking.*
1
Enable manual control of horizontal phase and frequency with TSTGFR[1:0] and
TSTGPH.
When TSTGEN == 1, these two bits control the horizontal frequency tracking.
00
Stop frequency tracking and freeze the frequency at the current value.*
01
Horizontal frequency tracks the input.
1X
Horizontal frequency tracking ignores video input and runs at nominal value based
on the field rate and output pixel rate selected by IFMT and PIXEL bits.
When TSTGEN == 1, this bit controls the horizontal phase tracking.
0
No phase tracking.*
1
Horizontal phase tracks the input video or HS1 input if in slave mode.
If TSTGE1 == 1, this bit controls AGC.
0
AGC clamps to back porch and gain is set based on sync tip-back porch difference.*
1
AGC clamps to sync tip and gain is set based on peak-valley difference.
Enables the function of TSTGPK.
0
Disables TSTGPK.*
1
Enables TSTGPK.
Vertical master mode.
0
Normal vertical sync operation.*
1
Vertical sync ignores input and free runs at 50 Hz or 60 Hz. This mode can be used
to generate video timing for a slave device.
ELECTRONICS
Modified on May/04/2000
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