S5D0127X01 Datasheet, PDF (12/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
1.2. VIDEO TRACKING AND TIMING GENERATION
When the S5D0127X01 is configured for analog video input, the chip tracks the video input and generates a
sampling clock that is line locked to the input video. The S5D0127X01 requires an external reference clock for
video tracking. This reference can be supplied via a crystal using the on chip crystal interface or any TTL
compatible source. These configurations are shown in Figure 5
1.2.1. Clock Input Timing Reference
The S5D0127X01 can use either a 24.576 MHz or a 26.8 MHz reference. However, it is recommended that the
24.576 MHz reference be used for CCIR 601 operation, and the 26.8 MHz reference be used for square pixel or
dual mode operation. Other specifications for the crystal are:
• Fundamental or third overtone
• Load capacitance of ~20 pF
• Series resistance of 40 Ω or less
• Frequency deviation of 50 ppm or less over operating temperature range
22 pF
22 pF
Optional for 3rd
harmonic crystal
8
XTALI
24.576 MHz
S5D0127X01
7 _XTALO
5.7 µH
391 pF
Using a Crystal
24.576 MHz
TTL Clock
8
XTALI
S5D0127X01
N. C.
7
XTALO
Using a Clock
Figure 5. Standard Clock Configurations
1.2.2. The Sampling Clock
The sampling clock is generated by multiplying the line rate by N. This ensures that samples are aligned
horizontally, vertically and in time. The required N factor for the S5D0127X01 is based upon the field rate (60 Hz or
50 Hz) and the desired sampling rates (CCIR 601 or square pixel). Field rate can be automatically detected and
can be monitored with the FFRDET bit in the STAT register. Manual control of the field rate can be controlled with
the MNFMT and IFMT bits. The PIXSEL bit in register CMDA selects CCIR 601 or square pixel. Table 3 shows the
constants for the various combinations of input formats and output pixel rates.
ELECTRONICS
Modified on May/04/2000
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