S5D0127X01 Datasheet, PDF (15/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Analog video input
Digital video output
Active video
Chip delay
HAVE
Blank
HAVB
HAV
HS1,2
HSE
HSB
FS_PULSE
SLICE
SYG
BPG
CBG
CBGW
FH2
Active video
Figure 6. Approximate Locations for the Horizontal Timing Signals
1.2.4. Vertical Timing
The vertical timing signals include VS, VAV, ODD, SCH, and PID.
The VS is used for identifying the first line of video in the vertical position. The VS leading edge can be
programmed to either track the incoming video’s serration pulses or to be aligned to the beginning of the video line
or half way, as shown in Figure 36 and Figure 37. If VALIGN = 0, the VS leading edge is based on the output of an
internal low pass filter, and its location is dependent on the noise conditions of the video input. The trailing edge of
VS is locked to either the beginning of the video line or half way. The half way location relative to the beginning of
the video line changes depending on current input standard and output format. If VALIGN = 1, the leading edge of
the VS is aligned to the beginning of the video line or half way. The trailing edge is always aligned to the beginning
of the video line. The VSE bit in the CMDA register can be programmed to shorten the VS falling edge by one
horizontal line.
The VAV signal is used for vertical cropping. The start and stop lines for VAV are programmable through the VAVB
and VAVE registers, respectively.
The ODD signal signifies the current field number. When ODD is active, the current field is 1 or 3 (or 5 or 7 if in PAL
mode). The leading and trailing edges of ODD can be aligned to either the leading edge of VS (VALIGN = 1) or the
trailing edge of VS (VALIGN = 0). The signal may be used in conjunction with SCH and PID to exactly identify the
ELECTRONICS
Modified on May/04/2000
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