S5D0127X01 Datasheet, PDF (10/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
CMDD register. Timing selection is through either SYNDIR or EAV bit.
HS1
VS
Timing
Control
MULTIMEDIA VIDEO
EXV[7:0]
Y
Data
Demux _C
From Luma ADC
From Chroma ADC
Luma
Processing
Chroma
Processing
Figure 3. 8-bit YCbCr Input Data Path
To Luma Scaler
To Chroma Scaler
By using an external pixel clock, the reference clock input at XTALI is no longer required. Additional register bits
have to be programmed for different selections of pixel clock and timing, which are detailed in Table 2. The
following register/bit-settings are required for digital video input:
INSEL[3:0] = 8, 9, A, or F.
TSTCGN = 1.
DMCTL[1:0] = 2 or 3.
UGAIN = 238.
BRT = 34.
SAT = 229.
RGBH = UNIT = PED = 1.
Table 2: Digital Video Input Pixel Clock and Timing Selection
Pixel Clock
TTL Timing
Embedded
Timing
CKDIR^*1 SYNDIR^*2 EAV^*3
Additional Register Programming
VMEN TSTGPH TSTGEN TSTGFR PIXSEL MNFMT
IFMT
0
0
0
1
0
1
3 0 if input 1 0 if input
data is at
is 50 Hz
0
0
1
0
1
1
3
square
1
video.
0
1
0
0
1
1
1
pixel
1
1 if input
rate.
is 60 Hz
1
0
0
1
0
1
3 1 if input 1 video.
is at
1
0
1
0
1
1
1
CCIR
1
1
1
0
0
1
1
1
601 rate.
1
*1_{: CKDIR = 0 - CK is output and is internally generated. CKDIR = 1 - CK is input from an external source.}
*2_{: SYNDIR = 0 - HS1 and VS are output. SYNDIR = 1 - HS1 and VS are inputs from external sources.}
*3_{: EAV = 0 - chip will not sync to embedded timing. EAV = 1 - chip will sync to embedded timing.}
Note: the combination X11 for CKDIR, SYNDIR, EAV is not valid.
ELECTRONICS
Modified on May/04/2000
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