S5D0127X01 Datasheet, PDF (56/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Index
08h
0Ch
Mnemonic
HS1E
HXTRA
HS1 End Control
bit 7
bit 6
bit 5
HAVB[10:8]
bit 4
bit 3
bit 2
HS1E[8:1]
HAVE[10:8]
bit 1
bit 0
HS1BE0 HS2BE0
HS1E[8:1] -
HS1BE0
If HS1 is programmed as an output, this 9-bit register defines the end location of the HS1
signal. The content of this register is a 2’s complement number which is used as an offset to the
default. The resolution for this register is 1 CK clock.
Index
09h
0Ch
Mnemonic
HS2B
HXTRA
HS2 Start Control
bit 7
bit 6
bit 5
HAVB[10:8]
bit 4
bit 3
bit 2
HS2B[8:1]
HAVE[10:8]
bit 1
bit 0
HS1BE0 HS2BE0
HS2B[8:1] -
HS2BE0
This 9-bit register defines the start location of the HS2 signal. The content of this register is a
2’s complement number which is used as an offset to the default HS2B location. The resolution
for this register is 1 CK clock.
Index
0Ah
0Ch
Mnemonic
HS2E
HXTRA
HS2 End Control
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
HAVB[10:8]
HS2E[8:1]
HAVE[10:8]
bit 1
bit 0
HS1BE0 HS2BE0
HS2E[8:1] -
HS2BE0
This 9-bit register defines the end location of the HS2 signal. The content of this register is a 2’s
complement number which is used as an offset to the default HS2E location. The resolution for
this register is 1 CK clock.
ELECTRONICS
Modified on May/04/2000
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