S5D0127X01 Datasheet, PDF (59/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Index Mnemonic bit 7
0x0F
LUMA
0
Luma Control Register
bit 6
UNIT
bit 5
RGBH
bit 4
PED
bit 3
HYBWR
bit 2
CTRAP
bit 1
bit 0
HYPK[1:0]
HYPK[1:0]
CTRAP
HYBWR
PED
RGBH
UNIT
Luminance horizontal peaking control around 3 MHz.
0
Less than nominal peaking.*
1
Nominal peaking.
2
Increased peaking.
3
Maximum peaking.
Chroma trap (notch filter) in the luma path.
0
No chroma trap. This mode is recommended for S-video or component video input.*
1
Chroma trap is enabled.
Luminance horizontal bandwidth reduction control.
0
Full bandwidth.*
1
Reduced bandwidth.
Enable gain correction for 7.5 blank-to-black setup (pedestal).
0
No pedestal. 0% = Y code 16. 100% = Y code 235.*
1
Gain adjusted for 7.5% blank-to-black setup (pedestal). 7.5% = Y code 16. 7.5% -
100% input produce Y code 16 - 235.
High gain to produce full range Y for 0% (or 7.5% if PED = 1) to 100% input.
0
Black (0% or 7.5%) to peak white(100%) input produce Y code 16 to 235.*.
1
Black (0% or 7.5%) to peak white(100%) input produce Y code 0 to 255.
When PED and RGBH are both set to a “1”, setting this bit to a “1” produces a unit gain for
CCIR 601 digital input (INPSL[1:0] = 1).
0
Luma DC gain is controlled by PED and RGBH as described for each bit.*
1
Luma DC gain is unity for CCIR 601 digital input.
ELECTRONICS
Modified on May/04/2000
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