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S5D0127X01 Datasheet, PDF (5/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PIN DESCRIPTION (Continued)
Pin Name
Pin #
Type
Description
EVAV(OENC1) 4
I/O Valid line flag. Polarity is programmable. Active when output video
line is valid. During reset, the pin is an input and the logic state of
this pin is latched into the OENC[1]register bit. Use a 10 kΩ resistor
for pull-up or pull-down.
ODD
22
O Odd field flag. Polarity is programmable. Active for fields 1 and 3.
PID
17
O PAL ID flag. High for phase alternating line.
OEN
15
I Digital video data, timing and clock output 3-state control.
CK
18
I/O Pixel clock. In normal decoding mode, this is an output. When the
EXV port is used as an input, this can be programmed as an input
pixel clock.
CK2
21
O Pixel output clock (rate is one half of CK) aligned to HAV signal.
CCDAT
73
O Sliced VBI data output. Data can be from Closed Caption, Teletext,
Intercast, or WSS type encoded data.
CCEN
74
O When high, this pin indicates that valid VBI data is being clocked out
at the CCDAT pin or at the digital video output.
MULTI-PURPOSE I/O PORTS AND TEST ENABLE
PORTA
58
I/O Multi-purpose I/O port.
SCH(PORTB) 24
I/O Multi-purpose I/O port.
TESTEN
57
I When tied to VDD, the chip is put into the test mode. For normal use,
this pin should be connected to VSS.
TEST
96
I When tied to VDD, the chip is put into the test mode. For normal use,
this pin should be connected to VSS.
REFERENCE AND COMPENSATION
VRT
77
I/O
ADC VRT compensation (requires an external 0.1 µF capacitor
connected to VSS).
VRB
78
I/O ADC VRB compensation (requires an external 0.1 µF capacitor
connected to VSS).
COMP2
97
I/O Internal 1.3 V reference (requires an external 0.1 µF capacitor
connected to VSS).
HOST INTERFACE
SCLK
75
I Serial clock for IIC host interface.
SDAT
72
I/O Serial data for IIC host interface.
AEX0 - AEX1 69 - 70
I Device ID selection for IIC host interface.
ELECTRONICS
Modified on May/04/2000
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