S5D0127X01 Datasheet, PDF (55/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Index
05h
0Ch
Mnemonic
HAVB
HXTRA
HAV Start Control
bit 7
bit 6
bit 5
HAVB[10:8]
bit 4
bit 3
bit 2
HAVB[7:0]
HAVE[10:8]
bit 1
bit 0
HS1BE0 HS2BE0
HAVB[10:0]
This 11-bit register is used to define the start location of the HAV signal relative to the sync tip
(for CVBS input, this is the composite video sync tip. For 8-bit CbYCr input, this is the leading
edge of the HS1 or EAV). The content of this register is a 2’s complement number which is
used as an offset to the default. The resolution for this register is 1 CK clock.
Index
06h
0Ch
Mnemonic
HAVE
HXTRA
HAV End Control
bit 7
bit 6
bit 5
HAVB[10:8]
bit 4
bit 3
bit 2
HAVE[7:0]
HAVE[10:8]
bit 1
bit 0
HS1BE0 HS2BE0
HAVE[10:0]
This 11-bit register is used to define the end location of the HAV signal relative to the sync tip.
The content of this register is a 2’s complement number which is used as an offset to the
default The resolution for this register is 1 CK clock.
Index
07h
0Ch
Mnemonic
HS1B
HXTRA
HS1 Start Control
bit 7
bit 6
bit 5
HAVB[10:8]
bit 4
bit 3
bit 2
HS1B[8:1]
HAVE[10:8]
bit 1
bit 0
HS1BE0 HS2BE0
HS1B[8:1] -
HS1BE0
If HS1 is programmed as an output, this 9-bit register defines the start location of the HS1
signal. The content of this register is a 2’s complement number which is used as an offset to the
default. The resolution for this register is 1 CK clock.
ELECTRONICS
Modified on May/04/2000
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