S5D0127X01 Datasheet, PDF (86/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
Index
0x3F
Command Register F
Mnemonic bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
CMDF CTRAPFSC VIPMODE EVAVY UVDLEN UVDLSL REGUD
bit 1
TASKB
bit 0
CBWI
CBWI
TASKB
REGUD
UVDLSL
UVDLEN
EVAVY
VIPMODE
CTRAPFSC
Chroma bandwidth increase. This function should be used for digital video input mode only.
0
Normal chroma bandwidth.*
1
Increased chroma bandwidth.
Select between task A and B as described in “VIP Specification V. 1.0”.
0
Select CCIR 656 timing codes (T-bit is always 1).*
1
Select between task A and B when VBI data is output. If active video is output, T-bit
is set to 1(task A). If VBI data is output, T-bit is set to 0 (task B).
Control register update control.
0
Registers are updated immediately after being written to.*
1
The following registers and register bits are updated only during the start of vertical
sync after they are written to:
Index 0x02, indices 0x17 through 0x1D, bit 0 of index 0x04, bits [2:0] and [6:4] of
index 0x0E.
U or V delay control when UVDLEN is set to 1.
0
V is delayed by 1 CK period.*
1
U is delayed by 1 CK period.
Enable the function of UVDLSL.
0
UVDLSL is disabled.*
1
UVDLSL is enabled.
Control the output of INVALY, INVALU, and INVALV codes when EVAV is inactive.
0
Output of these codes are not affected by EVAV.*
1
These codes are output when EVAV is inactive (line is being dropped by the vertical
scaler).
Allows transfer of hardware sliced VBI data as ancillary data during the following line’s
horizontal blanking period.
0
Standard S5D0124D01 original sliced VBI data transfer.*
1
Optional ancillary sliced VBI data transfer.
Enable chroma trap location based on Fsc frequency instead of field rate.
0
Chroma trap based on field rate (same as S5D0124D01).*
1
Chroma trap based on detected Fsc frequency.
ELECTRONICS
Modified on May/04/2000
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