S5D0127X01 Datasheet, PDF (20/96 Pages) Samsung semiconductor – MULTISTANDARD VIDEO DECODER/SCALER

S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
For CCIR 601 digital video input (INPSL[1:0] = 1), register UNIT must be set to 1 to produce unit gain.
1.3.2. Horizontal Luma Frequency Shaping
The luma path contains many programmable filters for different purposes. The combination of these filters will give
different frequency characteristics.
The over sampled video data from the ADC pass through a decimation filter. The decimation filter has user
programmable bandwidth. Three registers are used to control the decimation filter characteristics and each is
designed for certain purposes. The HYBWI, when set to “1”, provides extra bandwidth for very high quality video
source. The HYBWR, when set to “1”, reduces the bandwidth so high frequency noise can be eliminated. The 3-bit
register HYLPF[2:0] provides the necessary bandwidth reduction for horizontal scaling. When all three registers
are programmed to “0”, the decimation filter has the bandwidth of the normal video. The S5D0127X01 provides the
option of bypassing the decimation filter. This option should be used only when the input video is band limited and
with low high frequency noise.
For composite video input, the notch filter can be enabled (CTRAP set to “1”) to extract the luminance. The notch
filter has different center frequencies for different input video format. User selectable peaking function is included
for edge enhancement. The notch filter should be bypassed for S-video and component video input, or if luma
comb filter is enabled.
The luminance filter characteristics have been designed to be very similar for all combinations of 60/50 Hz video
and CCIR 601/square pixel sampling rates. Figure 13 and Figure 14 show the output characteristics of the
luminance path with different filter combinations for the supported input standards and output pixel rates.
ELECTRONICS
Modified on May/04/2000
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