K4S643232C Datasheet, PDF (9/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
Command
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
,
A9 ~ A0
Note
Register
Mode register set
H
X
LL
L
L
X
OP code
1,2
Auto refresh
H
3
H
LL
LHX
X
Entry
L
3
Refresh
Self
refresh
Exit
L
H
H
H
L
H
X
X
3
HX
X
X
3
Bank active & row addr.
H
X
LL
HH X
V
Row address
Read &
Auto precharge disable
column address _{Auto precharge enable}
H
X
LH
L
H
X
V
L
Column
4
address
H
(A0 ~ A7)
4,5
Write &
Auto precharge disable
column address _{Auto precharge enable}
H
X
LH
L
L
X
V
L
Column
4
address
H
(A0 ~ A7)
4,5
Burst Stop
H
X
LH HL
X
X
6
Precharge
Bank selection
All banks
V
L
H
X
LL
HL
X
X
X
H
HX
X
X
Clock suspend or
active power down
Entry
H
L
X
L
V
V
V
X
Exit
L
H
XX
X
X
X
HX
X
X
Entry
H
L
X
Precharge power down mode
LH HH
X
HX
X
X
Exit
L
H
X
L
V
V
V
DQM
H
X
V
X
7
No operation command
HX
X
X
H
X
X
X
LH HH
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes :1. OP Code : Operand code
A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
-9-
REV. 1.1 Nov. '99