K4S643232C Datasheet, PDF (31/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
Page Write Cycle at Different Bank @Burst Length=4
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note 2
ADDR
RAa
RBb CAa
CBb RCc
RDd CCc
CDd
BA0
BA1
A10/AP
RAa
RBb
RCc
RDd
DQ
WE
DQM
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
tCDL
tRDL *Note 3
*Note 1
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Row Active
(D-Bank)
Row Active
(C-Bank)
Write
(C-Bank)
Write
(D-Bank)
Precharge
(All Banks)
: Don't care
*Note :
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
3.For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency
- 31
REV. 1.1 Nov. '99