K4S643232C Datasheet, PDF (24/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
CMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 2)
Current
State
CKE
(n-1)
CKE
n
CS
RAS
CAS
WE
ADDR
ACTION
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self Refresh --> Idle after tRFC (ABI)
Self
L
H
L
H
H
H
Refresh
L
H
L
H
H
L
L
H
L
H
L
X
X
Exit Self Refresh --> Idle after tRFC (ABI)
X
ILLEGAL
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self Refresh)
H
X
X
X
X
X
X
INVALID
All
L
H
H
X
X
X
Banks
L
H
L
H
H
H
Precharge
L
H
L
H
H
L
Power
L
H
L
H
L
X
Down
L
H
L
L
X
X
X
Exit Power Down --> ABI
X
Exit Power Down --> ABI
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Low Power Mode)
H
H
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
All
H
L
L
H
L
X
Banks
Idle
H
L
L
L
H
H
H
L
L
L
L
H
X
ILLEGAL
X
ILLEGAL
RA
Row (& Bank) Active
X
Enter Self Refresh
H
L
L
L
L
L
OP Code Mode Register Access
L
L
X
X
X
X
X
NOP
Any State
H
H
X
X
X
X
other than
H
L
X
X
X
X
Listed
L
H
X
X
X
X
above
L
L
X
X
X
X
X
Refer to Operations in Table 1
X
Begin Clock Suspend next cycle
X
Exit Clock Suspend next cycle
X
Maintain Clcok Suspend
Abbreviations : ABI = All Banks Idle, RA = Row Address
*Note : 6. CKE low to high transition is asynchronous.
7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + tSS must be satisfied before any command other than exit.
8. Power down and self refresh can be entered only from the both banks idle state.
9. Must be a legal command.
Note
6
6
7
7
8
8
8
9
9
- 24
REV. 1.1 Nov. '99