K4S643232C Datasheet, PDF (28/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
Read & Write Cycle at Same Bank @Burst Length=4
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
tRCD
*Note 1
tRC
HIGH
RAS
CAS
ADDR
Ra
Ca
BA0
*Note 2
Rb
Cb
BA1
A10/AP
Ra
CL=2
DQ
CL=3
tRAC
*Note 3
tRAC
*Note 3
Rb
tOH
Qa0 Qa1 Qa2 Qa3
tSAC
tSHZ *Note 4
tOH
Qa0 Qa1 Qa2 Qa3
tSAC
tSHZ *Note 4
Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3
tRDL
*Note 5
tRDL
*Note 5
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active Write
(A-Bank) (A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency
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REV. 1.1 Nov. '99