K4S643232C Datasheet, PDF (39/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
Burst Read Single bit Write Cycle @Burst Length=2
CMOS SDRAM
CLOCK
CKE
01
*Note 1
23
45
67
8 9 10 11 12 13 14 15 16 17 18 19
HIGH
CS
RAS
CAS
*Note 2
ADDR
RAa
BA0
CAa RBb CAb
RCc
CBc
CCd
BA1
A10/AP
RAa
RBb
RAc
CL=2
DQ
CL=3
DAa0
DAa0
QAb0 QAb1
QAb0 QAb1
DBc0
DBc0
QCd0 QCd1
QCd0 QCd1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Write with
Auto Precharge
(B-Bank)
Precharge
(C-Bank)
: Don't care
*Note :
1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
- 39
REV. 1.1 Nov. '99