K4S643232C Datasheet, PDF (38/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
CMOS SDRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa
DQ
tBDL
DAa0 DAa1 DAa2 DAa3 DAa4
*Note 2,4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
tRDL
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop Write
(A-Bank)
Precharge
(A-Bank)
*Note :
: Don't care
1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC
parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency.
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REV. 1.1 Nov. '99