K4S643232C Datasheet, PDF (7/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Value
AC input levels (Vih/Vil)
2.4/0.4
Input timing measurement reference level
1.4
Input rise and fall time
tr/tf = 1/1
Output timing measurement reference level
1.4
Output load condition
See Fig. 2
3.3V
Output
870Ω
1200Ω
50pF^*1
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
CMOS SDRAM
Z0 = 50Ω
Unit
V
V
ns
V
Vtt = 1.4V
50Ω
50pF^*1
(Fig. 1) DC output load circuit
Note : 1. The DC/AC Test Output Load of K4S643232C-55/60/70 is 30pF.
2. The VDD condition of K4S643232C-55/60 is 3.135V~3.6V.
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
CL
tCC(min)
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Row cycle time in Auto refresh
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
tRFC(min)
tRDL(min)
tCDL(min)
tBDL(min)
Col. address to col. address delay
tCCD(min)
Mode Register Set cycle time
tMRS(min)
Number of valid output data
CAS Latency=3
CAS Latency=2
-55
32
5.5 -
3-
3-
7-
10 -
12 -
-60
32
6-
3-
3-
7-
10 -
12 -
Version
-70
32
7-
2
3-
3-
7-
100
10 -
10 -
2
1
1
1
2
2
1
-80
32
8 10
-10
32
10 12
3 2 22
3 2 22
6 5 54
9 7 76
9 7 76
Unit
CLK
ns
CLK
CLK
CLK
CLK
us
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ea
Note
1
1
1
1
1
1,6
2, 5
2
2
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
-7-
REV. 1.1 Nov. '99