K4S643232C Datasheet, PDF (16/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
CMOS SDRAM
3. CAS Interrupt (I)
Note 1
1) Read interrupted by Read (BL=4)
CLK
CMD
ADD
DQ(CL2)
DQ(CL3)
RD RD
AB
QA0 QB0 QB1 QB2 QB3
tCCD
Note 2
QA0 QB0 QB1 QB2 QB3
2) Write interrupted by Write (BL=2)
CLK
CMD
ADD
WR WR
tCCD Note 2
AB
DQ
DA0 DB0 DB1
tCDL
Note 3
3) Write interrupted by Read (BL=2)
DQ(CL2)
DQ(CL3)
WR RD
tCCD Note 2
AB
DA0
DA0
tCDL
Note 3
QB0 QB1
QB0 QB1
*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
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REV. 1.1 Nov. '99