K4S643232C Datasheet, PDF (18/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
CMOS SDRAM
5. Write Interrupted by Precharge & DQM
CLK
CMD
WR
DQM
Note 3,4
PRE
Note 2
DQ
D0 D1 D2 D3
Masked by DQM
*Note : ^{1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.}
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of four banks operation.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency.
6. Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
WR
PRE
D0 D1 D2 D3
tRDL
Note 1,4
2) Normal Read (BL=4)
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
PRE
Note 2
1
Q0 Q1 Q2 Q3
2
Q0 Q1 Q2 Q3
7. Auto Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
WR
D0 D1 D2 D3
Note 3,4
Auto Precharge Starts
2) Normal Read (BL=4)
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
D0 D1 D2 D3
D0 D1 D2 D3
Note 3
Auto Precharge Starts
*Note : 1. tRDL : Last data in to row precharge delay
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency
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REV. 1.1 Nov. '99