K4S643232C Datasheet, PDF (42/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
Mode Register Set Cycle
Auto Refresh Cycle
CMOS SDRAM
0 1 2 3 4 5 6 7 8 90 110 121 132 143 154 165 176 187 198 109
CLOCK
CKE
HIGH
HIGH
CS
RAS
*Note 2
tRFC
CAS
*Note 1
ADDR
*Note 3
Key
Ra
DQ
Hi-Z
Hi-Z
WE
DQM
¡ó
¡ó
MRS
New
Command
Auto Refresh
New Command
: Don't care
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
*Note :
MODE REGISTER SET CYCLE
1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
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REV. 1.1 Nov. '99