K4S643232C Datasheet, PDF (29/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
Page Read & Write Cycle at Same Bank @Burst Length=4
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
tRCD
RAS
CAS
*Note 2
ADDR
Ra
Ca
Cb
Cc
Cd
BA0
BA1
A10/AP
Ra
CL=2
DQ
CL=3
WE
DQM
Qa0 Qa1 Qb0 Qb1 Qb2
tRDL *Note 4
Dc0 Dc1 Dd0 Dd1
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0 Dd1
tCDL
*Note 1
*Note 3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency
- 29
REV. 1.1 Nov. '99