K4S643232C Datasheet, PDF (5/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System clock
CS
Chip select
CKE
Clock enable
A0 ~ A10
Address
BA0,1
Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 3 Data input/output mask
DQ0 ~ 31
VDD/VSS
Data input/output
Power supply/ground
VDDQ/VSSQ Data output power/ground
NC
No Connection
CMOS SDRAM
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
DQ0 ~ DQ31
Symbol
Min
CCLK
2.5
CIN
2.5
CADD
2.5
COUT
4.0
Max
4
4.5
4.5
6.5
Unit
V
V
°C
W
mA
Unit
pF
pF
pF
pF
-5-
REV. 1.1 Nov. '99