K4S643232C Datasheet, PDF (19/43 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232C
8. Burst Stop & Interrupted by Precharge
1) Normal Write (BL=4)
CLK
CMD
DQM
DQ
WR
PRE
D0 D1 D2 D3
tRDL Note 1,5
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
RD
PRE
Note 3
DQ(CL2)
1
Q0 Q1
DQ(CL3)
2
Q0 Q1
CMOS SDRAM
2) Write Burst Stop (BL=8)
CLK
CMD
DQM
DQ
WR
STOP
D0 D1 D2 D3 D4 D5
tBDL Note 2
4) Read Burst Stop (BL=4)
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
STOP
1
Q0 Q1
2
Q0 Q1
9. MRS
1) Mode Register Set
CLK
CMD
Note 4
PRE
tRP
MRS
ACT
2CLK
*Note : 1. tRDL : 1 CLK
2. tBDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : All banks precharge if necessary.
MRS can be issued only at all banks precharge state.
5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency
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REV. 1.1 Nov. '99