K5A3X40YTC Datasheet, PDF (44/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Preliminary
MCP MEMORY
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
Address
CS1_S
CS2_S
UB, LB
WE
Data in
tAS(3)
tWC
tCW(2)
tAW
tCW(2)
tBW
tWP(1)
tWR(4)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1_S and low WE. A write begins when CS1_S goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1_S goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1_S going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1_S or WE going high.
SRAM DATA RETENTION WAVE FORM
CS1_S controlled
Vcc_S
2.7V
tSDR
Data Retention Mode
tRDR
2.2V
VDR
CS1_S
Vss
CS2_S controlled
Vcc_S
2.7V
CS2_S
VDR
0.4V
Vss
CS1_S≥Vcc_S - 0.2V
Data Retention Mode
tSDR
CS2_S≤0.2V
tRDR
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Revision 0.0
November 2002