K5A3X40YTC Datasheet, PDF (38/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS
Toggle Bit During Internal Routine Operation
tAHT
tAS
Address*
tASO
tAHT
CE_F
tOEH2
tCEPH
WE
OE
DQ6/DQ2
tDH
Data In
tOEPH
Status
Data
tOE
Status
Data
Preliminary
MCP MEMORY
Status
Data
Array Data Out
RY/BY
WE
DQ6
NOTE: Address for the write operation must include a bank address (A19~A20) where the data is written.
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ2
Toggle
DQ2 and DQ6
with OE or CE_F
NOTE: DQ2 is read from the erase-suspended block.
Parameter
Output Enable Access Time
OE Hold Time
Address Hold Time
Address Setup
Address Setup Time
Data Hold Time
CE_F High during toggle bit polling
OE High during toggle bit polling
Symbol
tOE
tOEH2
tAHT
tASO
tAS
tDH
tCEPH
tOEPH
70ns
Min
Max
-
25
10
-
0
-
55
-
0
-
0
-
20
-
20
-
80ns
Min
Max
-
25
10
-
0
-
55
-
0
-
0
-
20
-
20
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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Revision 0.0
November 2002