K5A3X40YTC Datasheet, PDF (22/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Preliminary
MCP MEMORY
Table 12. Common Flash Memory Interface Code
Description
Query-unique ASCII string "PRI"
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock(Bits 1-0)
0 = Required, 1= Not Required
Silcon Revision Number(Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Block Protect
0 = Not Supported, 1 = Number of blocks in per group
Block Temporary Unprotect 00 = Not Supported, 01 = Supported
Block Protect/Unprotect scheme 04=K8D1x16U mode
Simultaneous Operation (1)
00 = Not Supported, XX = Number of Blocks in Bank2
Burst Mode Type 00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page
ACC(Acceleration) Supply Minimum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
ACC(Acceleration) Supply Maximum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
Top/Bottom Boot Block Flag
02H = Bottom Boot Device, 03H = Top Boot Device
NOTE:
1. The number of blocks in Bank2 is device dependent.
K5A3240Y(8Mb/24Mb) = 30h (48blocks)
K5A3340Y(16Mb/16Mb) = 20h (32blocks)
Addresses
(Word Mode)
40H
41H
42H
43H
44H
Addresses
(Byte Mode)
80H
82H
84H
86H
88H
45H
8AH
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
8CH
8EH
90H
92H
94H
96H
98H
9AH
9CH
9EH
Data
0050H
0052H
0049H
0033H
0033H
0000H
0002H
0001H
0001H
0004H
00XXH
0000H
0000H
0085H
00C5H
000XH
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Revision 0.0
November 2002