K5A3X40YTC Datasheet, PDF (31/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS
Hardware Reset/Read Operations
Preliminary
MCP MEMORY
Address
CE_F
RESET
Outputs
tRH
tRP
tRH
High-Z
tRC
Address Stable
tAA
tCE
tOH
Output Valid
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold Time from Address, CE_F or OE
RESET Pulse Width
RESET High Time Before Read
Symbol
tRC
tAA
tCE
tOH
tRP
tRH
70ns
Min
Max
70
-
-
70
-
70
0
-
500
-
50
-
80ns
Unit
Min
Max
80
-
ns
-
80
ns
-
80
ns
0
-
ns
500
-
ns
50
-
ns
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Revision 0.0
November 2002