K5A3X40YTC Datasheet, PDF (10/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Preliminary
MCP MEMORY
Table 8. SRAM Operation Table
1. Word Mode
CS1_S CS2_S
OE
H
X
X
WE
BYTE_S
SA
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
L
H
H
H
Vcc_S
X
L
H
H
H
Vcc_S
X
L
H
L
H
Vcc_S
X
L
H
L
H
Vcc_S
X
L
H
L
H
Vcc_S
X
L
H
X
L
Vcc_S
X
L
H
X
L
Vcc_S
X
L
H
X
L
Vcc_S
X
NOTE: X means don′t care. (Must be low or high state)
2. Byte Mode
CS1_S CS2_S
OE
H
X
X
WE
BYTE_S
SA
X
X
X
X
L
X
X
X
X
L
H
H
H
VSS
SA¹⁾
L
H
L
H
VSS
SA¹⁾
L
H
X
L
VSS
SA¹⁾
NOTE: X means don′t care. (Must be low or high state)
DNU = Do Not Use
1) Address input for byte operation.
LB
X
X
H
L
X
L
H
L
L
H
L
LB
X
X
DNU
DNU
DNU
UB
X
X
H
X
L
H
L
L
H
L
L
UB
X
X
DNU
DNU
DNU
D/Q0~7
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
D/Q8~15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Deselected
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
D/Q0~7
High-Z
High-Z
High-Z
Dout
Din
D/Q8~15
High-Z
High-Z
DNU
DNU
DNU
Mode
Deselected
Deselected
Output Disabled
Lower Byte Read
Lower Byte Write
Power
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Power
Standby
Standby
Active
Active
Active
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Revision 0.0
November 2002