K5A3X40YTC Datasheet, PDF (34/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Preliminary
MCP MEMORY
Flash SWITCHING WAVEFORMS
Word to Byte Timing Diagram for Read Operation
CE_F
tCE
OE
BYTE
DQ0-DQ7
DQ8-DQ14
tELFL
Data Output
(DQ8-DQ14)
DQ15/A-1
Data Output
(DQ15)
tFLQZ
Byte to Word Timing Diagram for Read Operation
Data Output
(DQ0-DQ7)
Address Input (A-1)
CE_F
tCE
OE
BYTE
DQ0-DQ7
DQ8-DQ14
tELFH
Data Output
(DQ0-DQ7)
Data Output
(DQ8-DQ14)
DQ15/A-1
Address Input
(A-1)
tFHQV
BYTE Timing Diagram for Write Operation
Data Output
(DQ15)
CE_F
WE
BYTE
Parameter
Chip Enable Access Time
CE_F to BYTE Switching Low or High
BYTE Switching Low to Output HIGH-Z
BYTE Switching High to Output Active
The falling edge of the last WE signal
tSET
(tAS)
tHOLD(tAH)
Symbol
tCE
tELFL/tELFH
tFLQZ
tFHQV
70ns
Min
Max
-
70
-
5
-
25
-
25
80ns
Min
Max
-
80
-
5
-
25
-
25
Unit
ns
ns
ns
ns
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Revision 0.0
November 2002