K5A3X40YTC Datasheet, PDF (37/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS
Data Polling During Internal Routine Operation
CE_F
OE
tOE
tOEH2
Preliminary
MCP MEMORY
tDF
WE
tCE
tOH
DQ7 ^{Data In}
DQ0-DQ6 _{Data In}
tPGM or tBERS
DQ7
Status Data
*DQ7 = Valid Data
Valid Data
NOTE: *DQ7=Vaild Data (The device has completed the internal operation).
HIGH-Z
HIGH-Z
RY/BY Timing Diagram During Program/Erase Operation
CE_F
WE
RY/BY
The rising edge of the last WE signal
Entire progrming
or erase operation
tBUSY
Parameter
Program/Erase Valid to RY/BY Delay
Chip Enable Access Time
Output Enable Time
CE_F & OE Disable Time
Output Hold Time from Address, CE_F or OE
OE Hold Time
Symbol
tBUSY
tCE
tOE
tDF
tOH
tOEH2
70ns
Min
Max
90
-
-
70
-
25
-
16
0
-
10
-
80ns
Unit
Min
Max
90
-
ns
-
80
ns
-
25
ns
-
16
ns
0
-
ns
10
-
ns
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Revision 0.0
November 2002