K5A3X40YTC Datasheet, PDF (39/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS
RESET Timing Diagram
High
RY/BY
CE_F or OE
tRH
RESET
tRP
RY/BY
CE_F or OE
RESET
tREADY
Reset Timings NOT during Internal Routine
tREADY
tRB
tRP
Reset Timings during Internal Routine
Power-up and RESET Timing Diagram
RESET
tRSTS
Vcc_F
Address
DATA
Parameter
RESET Pulse Width
RESET Low to Valid Data
(During Internal Routine)
RESET Low to Valid Data
(Not during Internal Routine)
RESET High Time Before Read
RY/BY Recovery Time
RESET High to Address Valid
RESET Low Set-up Time
tAA
Symbol
tRP
tREADY
tREADY
tRH
tRB
tRSTW
tRSTS
70ns
Min
Max
500
-
-
20
-
500
50
-
0
-
200
-
500
-
Preliminary
MCP MEMORY
80ns
Unit
Min
Max
500
-
ns
-
20
µs
-
500
ns
50
-
ns
0
-
ns
200
-
ns
500
-
ns
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Revision 0.0
November 2002