K5A3X40YTC Datasheet, PDF (30/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS
Read Operations
Preliminary
MCP MEMORY
Address
tRC
Address Stable
tAA
CE_F
OE
WE
Outputs
HIGH-Z
tOE
tOEH1
tCE
tDF
tOH
Output Valid
HIGH-Z
RY/BY
HIGH
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Time
CE_F & OE Disable Time (1)
Output Hold Time from Address, CE_F or OE
OE Hold Time
NOTE: 1. Not 100% tested.
Symbol
tRC
tAA
tCE
tOE
tDF
tOH
tOEH1
70ns
Min
Max
70
-
-
70
-
70
-
25
-
16
0
-
0
-
80ns
Unit
Min
Max
80
-
ns
-
80
ns
-
80
ns
-
25
ns
-
16
ns
0
-
ns
0
-
ns
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Revision 0.0
November 2002