K5A3X40YTC Datasheet, PDF (32/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Preliminary
MCP MEMORY
Flash SWITCHING WAVEFORMS
Alternate WE Controlled Program Operations
tAS
Data Polling
Address
555H
PA
PA
tAH
CE_F
OE
tCH
WE
DATA
RY/BY
tOES
tWC
tWP
tWPH
tCS
tDH
A0H
tDS
tPGM
PD
tBUSY
Status DOUT
tRB
tRC
tOE
tDF
tCE
tOH
NOTES: 1. DQ7 is the output of the complement of the data written to the device.
2. DOUT is the output of the data written to the device.
3. PA : Program Address, PD : Program Data
4. The illustration shows the last two cycles of the program command sequence.
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
CE_F Setup Time
CE_F Hold Time
OE Setup Time
Write Pulse Width
Write Pulse Width High
Programming Operation
Word
Byte
Accelerated Programming Operation
Word
Byte
Read Cycle Time
Chip Enable Access Time
Output Enable Time
CE_F & OE Disable Time
Output Hold Time from Address, CE_F or OE
Program/Erase Valide to RY/BY Delay
Recovery Time from RY/BY
Symbol
tWC
tAS
tAH
tDS
tDH
tCS
tCH
tOES
tWP
tWPH
tPGM
tACCPGM
tRC
tCE
tOE
tDF
tOH
tBUSY
tRB
70ns
Min
Max
70
-
0
-
45
-
35
-
0
-
0
-
0
-
0
-
35
-
25
-
14(typ.)
9(typ.)
9(typ.)
7(typ.)
70
-
-
70
-
25
-
16
0
-
90
-
0
-
80ns
Min
Max
80
-
0
-
45
-
35
-
0
-
0
-
0
-
0
-
35
-
25
-
14(typ.)
9(typ.)
9(typ.)
7(typ.)
80
-
-
80
-
25
-
16
0
-
90
-
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
µs
µs
ns
ns
ns
ns
ns
ns
ns
- 32 -
Revision 0.0
November 2002