K5A3X40YTC Datasheet, PDF (33/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Preliminary
MCP MEMORY
Flash SWITCHING WAVEFORMS
Alternate CE_F Controlled Program Operations
tAS
Address
555H
PA
tAH
WE
OE
CE_F
tOES
tWC
tCP
tWS
tCPH
tDH
DATA
RY/BY
A0H
PD
tDS
Data Polling
tPGM
tBUSY
PA
Status DOUT
tRB
NOTES:
1. DQ7 is the output of the complement of the data written to the device.
2. DOUT is the output of the data written to the device.
3. PA : Program Address, PD : Program Data
4. The illustration shows the last two cycles of the program command sequence.
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
OE Setup Time
WE Setup Time
WE Hold Time
CE_F Pulse Width
CE_F Pulse Width High
Programming Operation
Accelerated Programming Operation
Program/Erase Valide to RY/BY Delay
Recovery Time from RY/BY
Word
Byte
Word
Byte
Symbol
tWC
tAS
tAH
tDS
tDH
tOES
tWS
tWH
tCP
tCPH
tPGM
tACCPGM
tBUSY
tRB
70ns
Min
Max
70
-
0
-
45
-
35
-
0
-
0
-
0
-
0
-
35
-
25
-
14(typ.)
9(typ.)
9(typ.)
7(typ.)
90
-
0
-
80ns
Min
Max
80
-
0
-
45
-
35
-
0
-
0
-
0
-
0
-
35
-
25
-
14(typ.)
9(typ.)
9(typ.)
7(typ.)
90
-
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
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Revision 0.0
November 2002